General information | |||||||
Type |
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Market segment | Server | ||||||
Family |
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CPU part numbers |
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Frequency | 133 MHz | ||||||
Package |
387-pin Modified Staggered Ceramic Pin Grid Array with gold plated heat spreader 2.66" x 2.46" (6.76 cm x 6.25 cm) |
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Socket | Socket 8 | ||||||
S-spec numbers | |||||||
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Architecture / Microarchitecture | |||||||
Microarchitecture | P6 | ||||||
Core stepping | B0 (Q0815) | ||||||
CPUID | 611 (Q0815) | ||||||
Manufacturing process |
0.6 and 0.35 micron 5.5 million transistors |
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Data width | 32 bit | ||||||
Data bus width | 64 bit | ||||||
Floating Point Unit | Integrated | ||||||
Level 1 cache size |
8 KB four-way set associative code 8 KB two-way set associative data |
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Level 2 cache size | 256 KB | ||||||
Pipeline | 12-stage | ||||||
Multiprocessing | Up to 4 processors | ||||||
Low power features |
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Electrical / Thermal parameters |